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dual - current output, parallel input, 16 - /14 - bit multiplying dacs with 4 - quadrant resistors data sheet ad5547 / ad5557 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of thir d parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their r espective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004 C 2012 analog devices, inc. all rights reserved. technical support www.analog.com features dual channel 16- bit resolution: ad5547 14- bit resolution: ad5557 2 - or 4 - quadrant, 6.8 mhz bw multiplying dac 1 lsb dnl 1 lsb inl operating supply volt age: 2.7 v to 5.5 v low noise: 12 nv/ hz low power: i dd = 10 a max 0.5 s settling time built - in r fb facilitates current - to - voltage conversion built - in 4 - quadrant resistors allow 0 v to C 10 v, 0 v to +10 v, or 10 v outputs 2 ma full - scale current 20%, with v ref = 10 v ext ended automotive operating temperature range ? 40c to +125c selectable zero - scale/midscale power - on presets compact 38 - lead tssop package applications automatic test equipment instrumentation digitally controlled calibration digital waveform generation functional block dia gram dac a d0..d15 or d0..d13 dac a dac b addr decode input register rs dac a register rs dac b register rs power on reset v dd r comb r com a r 1a r ofs a v re f a r 1b r ofsb 04452-013 r fb a agnd a agndb v refb i ou t a r fbb i outb d0 t o d15 (ad5547) d0 t o d13 (ad5557) a0, a1 msb ldac dgnd wr rs input register rs dac b ad5547/ad5557 figure 1. general description the ad5547 / ad5557 are dual precision, 16 - /14 - bit, multiplying, low power, current - output, parallel input, digital - to - analog converters (dacs) . they are designed to operate from single +5 v supply with 10 v multiplying references for 4 - quadrant outputs with 6.8 mhz bandwidth. t he built - in , 4 - quadrant resistors facilitate resistance mat ching and temperature tracking, which minimize the number of components needed for multiquadrant applications. in addition, the feedback resistor (r fb ) simplifies the i - to - v conversion with an external buffer. the ad5547 / ad5557 are available in a compact , 38 - lead tssop package and operate at the extended automotive temperature range of ? 40 c to +125c. vref ?vref ?vref t o +vref 04452-002 u1 c1 r 1a 16/14 d at a r com a r1 r2 r ofs a r fb a c2 rfb rofs 16-/14-bit dac a msb a0, a1 2 power-on reset ad5547/ad5557 iou t a agnd a (one channe l shown on l y) u2 vou t a v re f a msb a0, a1 ldac wr rs wr rs ldac figure 2 . 16 - /14 - bit 4 - quadrant multiplying dac with minimum of external components (only one channel is shown)
ad5547/ad5557 data sheet rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ........................................... 10 circuit operation ........................................................................... 12 dac section ................................................................................ 12 digital section ............................................................................ 13 pcb layout, power supply bypassing, and ground connections ................................................................................ 13 applications information .............................................................. 14 unipolar mode ........................................................................... 14 bipolar mode .............................................................................. 16 reference selection .................................................................... 18 amplifier selection .................................................................... 18 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 11/12 rev. c to rev. d changes to figure 22 ...................................................................... 15 11/11 rev. b to rev. c added figure 14; renumbered sequentially .............................. 11 4 /10 rev. a to rev. b chan ges to features section and general description section . 1 changes to table 1 ............................................................................ 3 deleted figure 17 and figure 18; renumbered sequentially ... 10 changes to figure 15 and figure 16 ............................................. 1 1 changes to figure 20 ...................................................................... 14 added reference selection section, amplifier selection section, table 10, and table 11; renumbered sequentially ..................... 18 added table 12 ............................................................................... 19 9/09 rev. 0 to rev. a changes to features section ............................................................ 1 changes to static performance, relative accuracy, grade: ad5547c parameter, table 1 .............................................. 3 changes to ordering guide .......................................................... 19 1/04 rev ision 0: initial version
data sheet ad5547/ad5557 rev. d | page 3 of 20 specifications electrical character istics v dd = 2.7 v to 5.5 v, i out = v irtual gnd, gnd = 0 v, v ref = ? 10 v to +10 v, t a = ? 40 c to +125c, unless otherwise noted. table 1 . parameter symbol test cond itions /comments min typ max unit static performance 1 resolution n ad5547 , 1 lsb = v ref /2 16 = 153 v at v ref = 10 v 16 bits ad5557 , 1 lsb = v ref /2 14 = 6 10 v at v ref = 10 v 14 bits relative accuracy inl grade: ad5557 c 1 lsb grade: ad5547 b 2 lsb grade: ad55 47c 1 lsb differential nonlinearity dnl monotonic 1 lsb output leakage current i out data = zero scale, t a = 25c 10 na data = zero scale, t a = t a maximum 20 na full - scale gain error g fse data = full scale 1 4 mv bipolar mode gain error g e data = full scale 1 4 mv bipolar mode zero - scale error g zse data = full scale 1 3 mv full - scale temp erature coefficient 2 tcv fs 1 ppm/c reference input v ref range v ref ? 18 +18 v ref input resistance ref 4 5 6 k ? r1 and r2 resistance r1 and r2 4 5 6 k ? r1 -to - r2 mismatch ( r1 to r2) 0.5 1.5 ? feedback and offset resistance r fb , r ofs 8 10 12 k ? input capacitance 2 c ref 5 pf analog output output current i out data = full scale 2 ma output capacitance 2 c out code dependent 200 pf logic input and output logic input low voltage v il v dd = 5 v 0.8 v v dd = 3 v 0.4 v logic input high voltage v ih v dd = 5 v 2.4 v v dd = 3 v 2.1 v input leakage current i il 10 a input capacitance 2 c il 10 pf interface timing 2 , 3 see figure 3 data to wr setup time t ds v dd = 5 v 20 ns v dd = 3 v 35 ns data to wr hold time t dh v dd = 5 v 0 ns v dd = 3 v 0 ns wr pulse width t wr v dd = 5 v 20 ns v dd = 3 v 35 ns ldac pulse width t ldac v dd = 5 v 20 ns v dd = 3 v 35 ns rs pulse width t rs v dd = 5 v 20 ns v dd = 3 v 35 ns wr to ldac d elay time t lwd v dd = 5 v 0 ns v dd = 3 v 0 ns
ad5547/ad5557 data sheet rev. d | page 4 of 20 parameter symbol test conditions/comments min typ max unit supply characteristics power supply range v dd range 2.7 5.5 v positive supply current i dd logic inputs = 0 v 10 a power dissipation p diss logic inputs = 0 v 0.055 mw power supply sensitivity p ss ?v dd = 5% 0.003 %/% ac characteristics 4 output voltage settling time t s to 0.1% of full scale, data cycles from zero scale to full scale to zero scale 0.5 s reference multiplying bw bw v ref = 100 mv rms, data = full scale 6.8 mhz dac glitch impulse q v ref = 0 v, midscale C 1 to midscale ?3.5 nv-s multiplying feedthrough error v out /v ref v ref = 100 mv rms, f = 10 khz ?78 db digital feedthrough q d wr = 1, ldac toggles at 1 mhz 7 nv-s total harmonic distortion thd v ref = 5 v p-p, data = full scale, f = 1 khz ?104 db output noise density e n f = 1 khz, bw = 1 hz 12 nv/hz analog crosstalk c at signal input at channel a and measures the output at channel b, f = 1 khz ?95 db 1 all static performance tests (except i out ) are performed in a closed-loop system using an external precision op97 i-to-v converter amplifier. the device r fb terminal is tied to the amplifier output. the +in pin of the op97 is grounded, and the i out of the dac is tied to the op97 s ?in pin. typical values represent average readings measured at 25c. 2 guaranteed by design; not subject to production testing. 3 all input control signals are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and ar e timed from a voltage level of 1.5 v. 4 all ac characteristic tests are perfor med in a closed-loop system using an ad8038 i-to-v converter amplifier except for thd where the ad8065 was used. timing diagram 04452-018 t wr t ds t dh t lwd t ldac t rs wr data ldac rs figure 3. ad5547 / ad5557 timing diagram
data sheet ad5547/ad5557 rev. d | page 5 of 20 absolute maximum rat ings table 2 . parameter rating v dd to gnd ? 0.3 v to +8 v r fb , r ofs , r1, r com , and vref to gnd ? 18 v to + 18 v logic inputs to gnd ? 0.3 v to +8 v v(i out ) to gnd ? 0.3 v to v dd + 0.3 v input current to any pin except supplies 50 ma thermal resistance ( ja ) 1 maximum junction temperature (t j max ) 150c operating tempera ture range ? 40c to +125c storage temperature range ? 65c to +150c lead temperature vapor phase, 60 s ec 215c infrared, 15 s ec 220c 1 package power dissipation = (t j max ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability. esd caution
ad5547/ad5557 data sheet rev. d | page 6 of 20 pin configurations a nd function descript ions ad5547 t op view (not to scale) d1 1 d0 2 r ofs a 3 r fb a 4 r 1a 5 v re f a 7 i ou t a 8 agnd a 9 dgnd 10 agnd a 1 1 i outb 12 v refb 13 r comb 14 r 1b 15 r fbb 16 r ofsb 17 18 a0 19 d2 38 d3 37 d4 36 d5 35 d6 34 d7 33 d8 32 d9 31 d10 30 vdd 29 d1 1 28 d12 27 d13 26 d14 25 d15 24 23 msb 22 ldac 21 a1 20 r com a 6 wr rs 04452-003 figure 4. ad5547 pin configuration table 3 . ad5547 pin function descriptions pin no. mnemonic function 1, 2, 24 to 28, 30 to 38 d0 to d15 digital input data bits d0 to d15. signal level must be v dd + 0.3 v. 3 r ofsa bipolar offset re sistor a. accepts up to 18 v. in 2 - quadrant mode, r ofsa ties to r fba . in 4 - quadrant mode, r ofsa ties to r 1a and the external reference. 4 r fba internal matching feedback resistor a. connects to the external op amp for i -to - v conversion. 5 r 1a 4 - quandran t resistor. in 2 - quadrant mode, r 1a shorts to the v re fa pin. in 4 - quadrant mode, r 1a ties to r ofsa . do not connect when operating in unipolar mode. 6 r coma center tap point of the two 4 - quadrant resistors, r 1a and r 2a . in 4 - quadrant mode, r coma ties to th e inverting node of the reference amplifier. in 2 - quadrant mode, r coma shorts to the associated v ref a pin. do not connect if operating in unipolar mode. 7 v r e fa dac a reference input in 2 - quadrant mode, r2 terminal in 4 - quadrant mode. in 2 - quadrant mode, v re fa is the reference input with constant input resistance vs. code. in 4 - quadrant mode, v re fa is driven by the external reference amplifier. 8 i outa dac a current output. connects to the inverting terminal of external precision i -to - v op amp for voltage output. 9 agnda dac a analog ground. 10 dgnd digital ground. 11 agndb dac b analog ground. 12 i outb dac b current output. connects to inverting terminal of external precision i - to - v op amp for voltage output. 13 v refb dac b reference input pin. estab lishes dac full - scale voltage. constant input resistance vs. code. if configured with an external op amp for 4 - quadrant multiplying, v refb becomes C v ref . 14 r comb center tap point of the two 4 - quadrant resistors, r 1b and r 2b . in 4 - quadrant mode, r comb tie s to the inverting node of the reference amplifier. in 2 - quadrant mode, r comb shorts to the v ref b pin. do not connect if operating in unipolar mode. 15 r 1b 4 - quandrant resistor. in 2 - quadrant mode, r 1b shorts to the v refb pin. in 4 - quadrant mode, r 1b ties to r ofsb . do not connect if operating in unipolar mode. 16 r fbb internal matching feedback resistor b. connects to external op amp for i - to - v conversion. 17 r ofsb bipolar offset resistor b. accepts up to 18 v. in 2 - quadrant mode, r ofsb ties to r fbb . in 4 - quadrant mode, r ofsb ties to r 1b and an external reference. 18 wr write control digital input in, active low. wr transfers shift register data to the dac register on the rising edge. signal level must be v dd + 0.3 v.
data sheet ad5547/ad5557 rev. d | page 7 of 20 pin no. mnemonic function 19 a0 address pin 0. signal level must be v dd + 0.3 v. 20 a1 address pin 1. signal level must be v dd + 0.3 v. 21 ldac digital input load dac control. signal level must be v dd + 0.3 v. 22 msb power - on reset state. msb = 0 corresponds to z ero - scale reset; msb = 1 corresponds to midscale reset. the signal level must be v dd + 0.3 v. 23 rs active low resets both input and dac registers. resets to zero - scale if msb = 0 and resets to midscale if msb = 1. signal level mus t be v dd + 0.3 v. 29 vdd positive power supply input. the specified range of operation is 2.7 v to 5.5 v.
ad5547/ad5557 data sheet rev. d | page 8 of 20 nc 1 nc 2 r ofs a 3 r fb a 4 r 1a 5 v re f a 7 i ou t a 8 agnd a 9 dgnd 10 agndb 1 1 i outb 12 v refb 13 r comb 14 r 1b 15 r fbb 16 r ofsb 17 18 a0 19 r com a 6 wr nc = no connect d0 38 d1 37 d2 36 d3 35 d4 34 d5 33 d6 32 d7 31 d8 30 vdd 29 d9 28 d10 27 d1 1 26 d12 25 d13 24 23 msb 22 ldac 21 a1 20 rs 04452-004 ad5557 t op view (not to scale) figure 5. ad5557 pin configuration table 4 . ad5557 pin function descriptions pin no. mnemonic function 1, 2 nc no connection. do not connect anything other than the dummy pads to these pins. 3 r ofsa bipolar offset resistor a. accepts up to 18 v. in 2 - quad rant mode, r ofsa ties to r fba . in 4 - quadrant mode, r ofsa ties to r 1a and the external reference. 4 r fba internal matching feedback resistor a. connects to the external op amp for i -to - v conversion. 5 r 1a 4 - quandrant resistor. in 2 - quadrant mode, r 1a shor ts to the v re fa pin. in 4 - quadrant mode, r 1a ties to r ofsa . do not connect when operating in unipolar mode. 6 r coma center tap point of the two 4 - quadrant resistors, r 1a and r 2a . in 4 - quadrant mode, r coma ties to the inverting node of the reference amplif ier. in 2 - quadrant mode, r coma shorts to the v ref a pin. do not connect if operating in unipolar mode. 7 v r e fa dac a reference input in 2 - quadrant mode, r2 terminal in 4 - quadrant mode. in 2 - quadrant mode, v re fa is the reference input with constant input re sistance vs. code. in 4 - quadrant mode, v re fa is driven by the external reference amplifier. 8 i outa dac a current output. connects to the inverting terminal of external precision i -to - v op amp for voltage output. 9 agnda dac a analog ground. 10 dgnd dig ital ground. 11 agndb dac b analog ground. 12 i outb dac b current output. connects to inverting terminal of external precision i - to - v op amp for voltage output. 13 v refb dac b reference input pin. establishes dac full - scale voltage. constant input resis tance vs. code. if configured with an external op amp for 4 - quadrant multiplying, v refb becomes C v ref . 14 r comb center tap point of the two 4 - quadrant resistors, r 1b and r 2b . in 4 - quadrant mode, r comb ties to the inverting node of the reference amplifier. in 2 - quadrant mode, r comb shorts to the v ref b pin. do not connect if operating in unipolar mode. 15 r 1b 4 - quandrant resistor. in 2 - quadrant mode, r 1b shorts to the v refb pin. in 4 - quadrant mode, r 1b ties to r ofsb . do not connect if operating in unipolar mode. 16 r fbb internal matching feedback resistor b. connects to external op amp for i - to - v conversion. 17 r ofsb bipolar offset resistor b. accepts up to 18 v. in 2 - quadrant mode, r ofsb ties to r fbb . in 4 - quadrant mode, r ofsb ties to r 1b and an external reference. 18 wr write control digital input in, active low. transfers shift register data to the dac register on the rising edge. signal level must be v dd + 0.3 v. 19 a0 address pin 0. signal level must be v dd + 0.3 v. 20 a1 address pin 1. signal level must be v dd + 0.3 v. 21 ldac digital input load dac control. signal level must be v dd + 0.3 v. 22 msb power - on reset state. msb = 0 corresponds to zero - scale reset; msb = 1 corresponds to midscale reset. the signal level must be v dd + 0.3 v.
data sheet ad5547/ad5557 rev. d | page 9 of 20 pin no. mnemonic function 23 rs active low resets both input and dac registers. resets to zero - scale if msb = 0 and resets to midscale if msb = 1. signal level must be v dd + 0.3 v. 24 to 28, 30 to 38 d13 to d0 digital input data bits d13 to d0. signal level must be v dd + 0.3 v. 29 vdd positive power supply input. the specified range of operation is 2.7 v to 5.5 v. table 5 . address decoder pins a1 a0 output update 0 0 dac a 0 1 none 1 0 dac a and dac b 1 1 dac b table 6 . control inputs rs wr ldac register operation 0 x x reset the output to 0 with msb = 0; reset the o utput to midscale with msb = 1. 1 0 0 load the input register with data bits. 1 1 1 load the dac register with the contents of the input register. 1 0 1 the input and dac registers are transparent. 1 when ldac and wr are tied toge ther and programmed as a pulse, the data bits are loaded into the input register on the falling edge of the pulse and are then loaded into the dac register on the rising edge of the pulse. 1 1 0 no register operation.
ad5547/ad5557 data sheet rev. d | page 10 of 20 typical performance characteristic s 1.0 0.8 0.6 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 in l ( lsb) code ( decimal) 04452-019 figure 6. ad5547 integral nonlinearity error 1.0 0.8 0.6 0 8192 16,384 24,576 32,768 40,960 49,152 57,344 65,536 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 dn l (lsb) code (decimal) 04452-020 figure 7. ad5547 differential nonlinearity error 1.0 0.8 0.6 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 in l (lsb) code (decimal) 04452-021 figu re 8. ad5557 integral nonlinearity error 04452-010 1.0 0.8 0.6 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 dn l (lsb) code (decimal) figure 9. ad5557 differential nonlinearity error 1.5 1.0 2 4 ge dn l in l 6 8 10 0.5 0 ? 0.5 ? 1.0 ? 1.5 linearit y error (lsb) supp l y vo lt age v dd (v) v ref = 2.5 v t a = 25 c 04452-022 figure 10 . linearity error vs. supply voltage, v dd 5 4 0 0.5 1.0 1.5 2.0 3.0 3.5 2.5 4.0 4.5 5.0 3 2 1 0 supp l y current i dd (lsb) logic input vo lt age v ih (v) v dd = 5 v t a = 25 c 04452-023 figure 11 . supply current vs. logic input voltage
data sheet ad5547/ad5557 rev. d | page 11 of 20 3.0 2.5 10k 100k 1m 10m 100m 2.0 1.5 1.0 0.5 0 supp l y current (ma) clock frequenc y (hz) 0x5555 0x8000 04452-024 0xffff 0x0000 figure 12 . ad5547 supply current vs. c lock frequency 04452-014 90 70 10 100 1k 10k 100k 1m 50 40 60 80 30 10 20 0 psrr (?db) frequenc y (hz) v dd = 5 v 10% v ref = 10v figure 13 . power supply rejection ratio (psrr) vs. frequency ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 5 10 15 20 25 frequenc y (khz) power spectrum (db) 04452- 1 14 figure 14 . ad5547/ad5557 analog t otal h armonic d istortion (thd) 04452-025 ldac v out 1 2 ch1 5.00v ch2 2.00v m 200ns a ch1 2.70v b ch1 ?6.20v 400.00ns figur e 15 . settling time from full scale to zero scale ?3.85 ?3.90 ?3.95 ?4.00 ?4.05 ?4.10 ?4.15 ?4.20 ?20 ?10 0 10 20 30 40 v out (v) time (ns) 04452-0016 figure 16 . ad5547 midscale transition and digital feedthrough 2 0 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 10k 100m gsin (db) frequency (hz) 04452-017 100k 1m 10m figure 17 . ad5547 unipolar reference multiplying bandwidth
ad5547/ad5557 data sheet rev. d | page 12 of 20 circuit operation d ac section the ad5547 / ad5557 are 16 - / 14 - bit, mul tiplying, current - output, parallel input dacs. the devices operate from a single 2.7 v to 5.5 v supply and provide both unipolar (0 v to C v ref or 0 v to +v ref ) and bipolar (v ref ) output ranges from C 18 v to +18 v references. in addition to the precision c onversion r fb commonly found in current output dacs, there are three addi - tional precision resistors for 4 - quadrant bipolar applications. the ad5547 / ad5557 consist of two groups of precision r - 2r ladders, which make up the 12/10 lsbs, re spectively. further more, the 4 msbs are decoded into 15 segments of resistor value 2r. figure 18 shows the architecture of the 16 - bit ad5547 . each of the 16 segments and the r - 2r ladder carries an equally weighted current of one - sixteenth of full scale. the feedback resistor r fb and 4 - quadrant resistor r ofs have values of 10 k? . each 4 - quadrant resis tor, r1 and r2, equals 5 k ? . in 4 - quadrant oper ation, r1, r2, and an external op amp work together to invert the reference voltage and apply it to the v ref input. with r ofs and r fb connected as shown in figure 2, the output can swing from ? v ref to +v ref . the reference voltage inputs exhibit a constant input resistance of 5 k? 20%. the impedance of i out , the dac output, is code dependent. external amplifier choice should take into account the variation of the a d5547 / ad5557 output impedance. the feedback resistance in parallel with the dac ladder resistance dominates output voltage noise. to maintain good analog performance, it is recommended that the power supply is bypassed with a 0.01 f to 0.1 f ceramic or chip capacitor in parallel with a 1 f tantalum capacitor. also, to minimize gain error, pcb metal traces between v ref and r fb should match. every code change of the dac corresponds to a step function; gain pea king at each output step may occur if the op amp has limited gbp and excessive parasitic capacitance present at the inverting node of the op amp. a compensation capacitor, therefore, may be needed between the i - to - v op amp inverting and output nodes to smo oth the step transition. such a compensation capacitor should be found empirically, but a 20 pf capacitor is generally adequate for the compensation. the v dd power is used primarily by the internal logic to drive the dac switches. note that the output prec ision degrades if the operating voltage falls below the specified voltage. users should also avoid using switching regulators because device power supply rejection degrades at higher frequencies. 04452-0 1 1 2r 80k? r 40k? 2r 80k? 2r 80k? 2r 80k? 2r 80k? 2r 80k? r 40k? 2r 80k? r 2r 80k? r 2r 80k? r 2r 80k? r 2r 80k? 2r 80k? r 40k? r2 5k? r1 5k? v ref 2r 80k? r 40k? 2r 80k? r 40k? 2r 80k? r 40k? 2r 80k? r 40k? 2r 80k? r 40k? 2r 80k? rcom r1 address decoder dac register input register ldac wr rs rs 4 msb 15 segments 8-bit r2r 4-bit r2r 15 8 4 ldac wr d15 d14 d0 rs 10k? 10k? rofs rfb iout agnd ra rb figure 18 . 16 - bit ad5547 equivalent r - 2r dac circuit with digital section, one channel shown
data sheet ad5547/ad5557 rev. d | page 13 of 20 digital section the ad5547 / ad5557 have 16 - /14 - bit par allel inputs. the devices are double buffered with 16 - /14 - bit registers. the double buffered feature allows the simultaneous update of several ad5547 s/ ad5557 s . for the ad5547 , the input register is loaded directly from a 16 - bit controller bus when wr is brought low. the dac register is updated with data from the input register when ldac is brought high . updating the dac register updates the dac output with the new data (see figure 18 ). to make both registers transparent, tie wr low and ldac high. the asynchronous rs pin resets the part to zero scale if msb = 0 and to midscale if msb = 1. esd protection circuits all logic input pins contain back - biased esd protection zeners connected to ground ( d gnd ) and v dd , as shown in figure 19. as a re sult, the voltage level of the logic input should not be greater than the supply voltage. 5k? digi t al inputs dgnd v dd 04452-026 figure 19 . equivalent esd protection circuits amplifier selection in addition to offset voltage, the bias current is important in op amp s election for precision current output dacs. a 30 na input bias current in the op amp contributes to 1 lsb in the full - scale error of the ad5547 . the op1177 and ad8628 op amps are good candidates for the i - to - v conversion. reference selection the initial accuracy and rated output of the voltage reference determine the full - span adjustment. the initial accuracy of the refe rence is usually a secondary concern because it can be trimmed. figure 25 shows an example of a trimming circuit. the zero - scale error can also be minimized by standard op amp nulling techniques. the voltage referen ce temperature coefficient (tc) and long - term drift are primary considerations. for example, a 5 v reference with a tc of 5 ppm/c means the output changes by 25 v/c. as a result, a reference operating at 55c contributes an additional 750 v full - scale error. similarly, the same 5 v reference with a 50 ppm long - term drift means the output may change by 250 v over time. therefore, it is practical to calibrate a system periodically to maintain its optimum precision. pcb layout, power su pply bypassing, a nd ground connections it is a g ood practi ce to employ a compact, minimum lead length , pcb layout design. the leads to the input should be as short as possible to minimize ir drop and stray inductance. the pcb metal traces between v ref and r fb should also be matched to minimize gain error. it is also essential to bypass the power supply with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f ta ntalum or electrolytic capacitors should also be applied at the supply in parallel with the ceramic capacitor to minimize transient disturbance and filter out low frequency ripple. to minimize the digital ground bounce, the ad5547 / ad5557 dgnd terminal should be joined with the agnd terminal at a single point. figure 20 illustrates the basic supply bypassing configuration an d agnd/dgnd connection for the ad5547 / ad5557 . v dd agnd dgnd c1 c2 5v + ? 1f 0.1f 04452-015 ad5547/ad5557 figure 20 . power supply bypassing
ad5547/ad5557 data sheet rev. d | page 14 of 20 applications information unipolar mode 2 - quadrant mul tiplying mode, v out = 0 v to C v ref the ad5547 / ad5557 dac architecture uses a current - steering r - 2r ladder design that requires an external reference and op amp to c onvert the unipolar mode of the output voltage to v out = ? v ref d /65,536 ( ad5547 ) (1) v out = ? v ref d /16,384 ( ad5557 ) (2) where d is the decimal equivalent of the input code. in this case, the output voltage polarity is opposite the v ref polarity (see figure 21 ). table 7 shows the negative output vs. code for the ad5547 . table 7 . ad5547 unipolar mode negative output vs. code d in binary v out (v) 1111 1111 1111 1111 C v ref (65,535/65,536) 1000 0000 0000 0000 C v ref /2 0000 0000 0000 0001 C v ref (1/65,536) 0000 0000 0000 0000 0 wr wr rs rs 2 ldac +2.5v 04452-007 ad8628 ad5547/ad5557 r 1a 16/14 d at a vdd r com a r2 u1 r1 r ofs a r fb a c6 rfb rofs msb a0, a1 i ou t a agnd a 6.8pf c1 1f c2 0.1f c3 0.1f v ou t a v re f a msb a0, a1 ldac +v ?v gnd 4 v out trim adr03 5 6 v in u3 2 +5v 16-/14-bit 2.5v c4 1f 0.1f c5 ?5v ?2.5v t o 0v figure 21 . unipolar 2 - quadrant multiplying mode, v out = 0 to ? v ref
data sheet ad5547/ad5557 rev. d | page 15 of 20 2 - quadrant multiplying mode, v out = 0 v to +v ref the ad5547 / ad5557 are designed to operate with either positive or negative reference voltages. as a result, a positive output can be achieved with an additional op amp, (see figure 22 ); the output becomes v out = +v ref d/65,536 ( ad5547 ) (3) v out = +v ref d/16,384 ( ad5557 ) (4) table 8 show s the positive output vs. code for the ad5547 . table 8 . ad5547 unipolar mode positive output vs. code d in binar v out v 1111 1111 1111 1 111 +v ref (65,535/65,536) 1000 0000 0000 0000 +v ref /2 0000 0000 0000 0001 +v ref (1/65,536) 0000 0000 0000 0000 0 c9 1f c8 0.1f ?5v wr wr rs rs 2 ldac ?2.5v +2.5v 0v t o +2.5v +5v 04452-005 ad8628 ad8628 ad5547/ad5557 c7 r 1a 16/14 d at a vdd r com a r2 r1 r ofs a r fb a c6 rfb rofs msb a0, a1 i ou t a agnd a u2b c4 1f 0.1f c1 1f c2 1f c3 0.1f c5 v ou t a v re f a msb a0, a1 ldac +v ?v gnd adr03 4 v out trim 5 6 v in u3 u2 2 +5v 16-/14-bit figure 22 . unipolar 2 - quadrant multiplying mode, v out = 0 to +v ref
ad5547/ad5557 data sheet rev. d | page 16 of 20 bipolar mode 4 - quadrant multiplying mode, v out = C v ref to +v ref the ad5547 / ad5557 contain on - chip all the 4 - quadrant resistors necessary for precision bipolar multiplying operation. such a feature minimizes the number of exponent components to only a voltage reference, dual op amp, and compensation capacitor (see figure 23 ). for example, with a +10 v reference, the circuit yields a precision, bipolar C 10 v to +10 v output . v out = ( d /32768 ? 1) v ref ( ad5547 ) (5) v out = ( d /16384 ? 1) v ref ( ad5557 ) (6) table 9 shows some of the results for the 16 - bit ad5547 . table 9 . ad5547 output vs. code d in binary v out 1111 1111 1111 1111 +v ref (32,767/32,768) 1000 0000 0000 0001 +v ref (1/32,768) 1000 0000 0000 0000 0 0111 1111 1111 1111 C v ref (1/32,768) 0000 0000 0000 0000 C v ref wr wr rs rs c6 0.1f c7 1 f 2 +10v ?10v ?15v ?10v t o +10v +15v 04452-006 ad8512 ad8512 ad5547/ad5557 c8 u2 a r 1a 16/14 d at a vdd r com a r2 u1 r1 r ofs a r fb a c9 rfb rofs msb a0, a1 i ou t a agnd a u2b c4 1f c1 1f c2 0.1f c3 0.1f c5 0.1 f vout v re f a msb a0, a1 ldac ldac +v ?v gnd adr01 4 v out trim 5 6 v in u3 2 +15v +5v 16-/14-bit dac a figure 23 . 4 - quadrant multiplying mode, v out = ? v ref to +v ref
data sheet ad5547/ad5557 rev. d | page 17 of 20 ac reference signal attenuator besides handling the digital waveform decoded from the parallel input data, the ad5547 / ad5557 can also handle low frequency ac reference signals for signal attenuation, channel equalization, and wavefo rm generation applications. the maximum signal range can be up to 18 v (see figure 24). system calibration the initial accuracy of the system can be adjusted by trimming the voltage reference adr0x with a digital pote ntiometer (see figure 25 ). the ad5170 provides a one - time programmable (otp), 8 - bit adjustment that is ideal and reliable for such calibration. a nalog devices, inc., otp dig ital potentiometer comes with programmable software that simplifies factory calibration. wr wr rs rs 2 ldac 04452-008 ad5547/ad5557 16/14 d at a vdd r ofs a r fb a c6 rfb rofs msb a0, a1 i ou t a agnd a c2 0.1f c1 1f v ou t a msb a0, a1 ldac +10v ?10v +5v op2177 c7 r 1a r com a r2 r1 v re f a 16-/14-bit c4 +15v u2b 1f 0.1f c5 c8 1f 0.1f c9 op2177 +v ?v u2 a u1 ?15v figure 24 . signal attenuator with ac reference wr wr rs rs 2 ldac 04452-009 ad5547/ad5557 16/14 d at a vdd r ofs a r fb a c6 rfb rofs msb a0, a1 i ou t a u2b +5v agnd a c1 1f c2 0.1f c3 0.1f v ou t a msb a0, a1 ldac ref 01/ad 4 5 10k? 1k? 6 u3 ad5170 r7 r3 +2.5v u4 u2 b 470k? 2 +5v 0v t o +2.5v ?2.5v ad8628 c7 r 1a r com a r2 u1 r1 v re f a 16-/14-bit gnd adr03 v out trim v in c4 1f 0.1f c5 ad8628 +v ?v figure 25 . full - span calibration
ad5547/ad5557 data sheet rev. d | page 18 of 20 reference selection when selecting a reference for use with the ad55xx series of current output dacs, pay attention to the output voltage, temperature coefficient specification of the reference. choosing a precision reference with a low output temperature coefficient minimizes er ror sources. table 10 lists some of the references available from analog devices, inc., that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current - s teering mode is an amplifier with low input bias currents and low input offset voltage. because of the code - dependent output resistance of the dac, th e input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this no ise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input offset voltage. this output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the dac to be nonmonotonic. the input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, r fb . common - mode rejection of the op amp is important in voltage - switching circuits because it produces a code - dependent error at the voltage output of the circuit. provided that the dac switches are driven from true wideband low impedance sources (v in and agnd), they sett le quickly. consequently, the slew rate and settling time of a voltage - switching dac circuit is determined largely by the output op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node (the voltage output node i n this application) of the dac. this is done by using low input capacitance buffer amplifiers and careful board design. analog devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in table 11 and table 12. table 10 . suitable analog devices precision references part no. output voltage (v) initial tolerance (%) maximum temperature drift (ppm/c) i ss (ma) outp ut noise (v p - p) package(s) adr01 10 0.05 3 1 20 soic -8 adr01 10 0.05 9 1 20 tsot - 5, sc70-5 adr02 5.0 0.06 3 1 10 soi c -8 adr02 5.0 0.06 9 1 10 tsot - 5, sc70-5 adr03 2.5 0.1 3 1 6 soic -8 adr03 2.5 0.1 9 1 6 tsot - 5, sc70 - 5 adr06 3.0 0.1 3 1 10 soic -8 adr06 3.0 0.1 9 1 10 tsot - 5, sc70-5 adr420 2.048 0.05 3 0.5 1.75 soic - 8, msop -8 adr421 2.50 0.04 3 0.5 1.75 soic - 8, msop -8 adr423 3.00 0.04 3 0.5 2 soic - 8, msop - 8 adr425 5.00 0.04 3 0.5 3.4 soic - 8, msop -8 adr431 2.500 0.04 3 0.8 3.5 soic - 8, msop -8 adr435 5.000 0.04 3 0.8 8 soic - 8, msop -8 adr391 2.5 0.16 9 0.12 5 tsot -5 adr395 5.0 0.10 9 0.12 8 tsot -5 table 11 . suitable analog devices precision op amps part no. supply voltage (v) v os maximum (v) i b maximum (na) 0.1 hz to 10 hz noise (v p - p) supply current (a) package(s) op97 2 to 20 25 0.1 0.5 600 soic - 8 , pdip -8 op1177 2.5 to 15 60 2 0.4 500 msop - 8, soic -8 ad867 5 5 to 18 75 2 0.1 2300 msop - 8, soic -8 ad8671 5 to 15 75 12 0.077 3000 msop - 8, soic -8 ada4004 -1 5 to 15 125 90 0.1 2000 soic - 8, sot -23-5 ad8603 1.8 to 5 50 0.001 2.3 40 tsot -5 ad8607 1.8 to 5 50 0.001 2.3 40 msop - 8, soic -8 ad8605 2.7 to 5 65 0.001 2.3 1000 wlcsp - 5, so t -23- 5 ad8615 2.7 to 5 65 0.001 2.4 2000 tsot -5 ad8616 2.7 to 5 65 0.001 2.4 2000 msop - 8, soic -8
data sheet ad5547/ad5557 rev. d | page 19 of 20 table 12 . suitable analog devices high s peed op amps part no. supply voltage (v) bw @ acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package(s) ad8065 5 to 24 145 180 1500 0.006 soic - 8, sot -23-5 ad8066 5 to 24 145 180 1500 0.006 soic - 8, msop -8 AD8021 5 to 24 490 120 1000 10,500 soic - 8, msop -8 ad8038 3 to 12 350 425 3000 750 soic - 8, sc70 -5 ada4899 5 to 12 600 310 35 100 lfcsp - 8, soic -8 ad8057 3 to 12 325 1000 5000 500 sot -23- 5, soic -8 ad8058 3 to 12 325 850 5000 500 soic - 8, msop -8 ad8061 2.7 to 8 320 650 6000 350 sot -23- 5, soic -8 ad8062 2.7 to 8 320 650 6000 350 soic - 8, msop -8 ad9631 3 to 6 320 1300 10,000 7000 soic - 8, pdip -8 table 13 lists the latest dacs available from analog devices. table 13 . adi current output dacs model bits ou tputs interface package comments ad5425 8 1 spi, 8 - bit load msop -10 fast 8 - bit load; see also ad5426 ad5426 8 1 spi msop -10 see also ad5425 fast load ad5450 8 1 spi tsot -8 see also ad5425 fast load ad5424 8 1 parallel tssop -16 ad5429 8 2 spi tssop - 16 ad5428 8 2 parallel tssop -20 ad5432 10 1 spi ms op -10 ad5451 10 1 spi tsot -8 ad5433 10 1 parallel tssop -20 ad5439 10 2 spi tssop -16 ad5440 10 2 parallel tssop -24 ad5443 12 1 spi msop -10 see also ad5452 and ad5444 ad5452 12 1 spi tsot -8 higher accuracy version of ad5443 ; see also ad5444 ad5445 12 1 parallel tssop -20 ad5444 12 1 spi msop -10 higher accuracy version of ad5443 ; see also ad5452 ad5449 12 2 spi tssop -16 ad5415 12 2 spi tssop -24 uncommitted resistors ad5447 12 2 parallel tssop -24 ad5405 12 2 parallel lfcsp -40 uncommitted resistors ad5453 14 1 spi tsot -8 ad5553 14 1 spi msop - 8 ad 5556 14 1 parallel tssop - 28 ad5446 14 1 spi msop -10 msop version of ad5453 ; compatible with ad5443 , ad5432 , and ad5426 ad5555 14 2 spi tssop -16 ad5557 14 2 parallel tssop -38 ad5543 16 1 spi msop -8 ad5546 16 1 parallel tssop -28 ad5545 16 2 spi tssop -16 ad5547 16 2 parallel tssop -38
ad5547/ad5557 data sheet rev. d | page 20 of 20 outline dimensions 3 8 2 0 1 9 1 9.80 9.7 0 9.6 0 pin 1 sea tin g plane 0.15 0.05 0.50 bsc 1.20 ma x 0.27 0.17 0.20 0.09 8 0 4.50 4.40 4.30 6.40 bsc 0.7 0 0.60 0.45 coplanarity 0.1 0 comp liant to jedec standard s mo-15 3-bd -1 figure 26 . 38 - lead thin shrink small outline package [tssop] (ru - 38) dimension s shown in millimeters ordering guide model 1 resolution (bits) dnl (lsb) inl (lsb) temperatur e range package description package option ordering quantity ad5547bru 16 1 2 ?40c to +125c 38- lead tssop ru -38 50 ad5547bru - reel7 16 1 2 ?40c to +125c 38- lead tssop ru -38 1,000 ad5547bruz 16 1 2 ?40c to +125c 38- lead tssop ru -38 50 ad5547cruz 16 1 1 ?40c to +125c 38 - lead tssop ru - 38 50 ad5547cruz - reel7 16 1 1 ?4 0c to +125c 38 - lead tssop ru - 38 1,000 ad5557cru 14 1 1 ?40c to +125c 38- lead tssop ru -38 50 ad5557cru - reel7 14 1 1 ?40c to +125c 38- lead tssop ru -38 1,000 ad5557cruz 14 1 1 ?40c to +125c 38- lead tssop ru -38 50 1 z = rohs compliant part. ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04452 - 0- 11/12(d)

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